Project Description
JRC-1, or Josh’s Retro Computer 1, is the first in the new JRC series of SBCs. The goal of the JRC project is to produce a powerful 65816-based system capable of playing the types of games that were prevalent in the mid to late 1980s. Each successive computer in the JRC line will move the design closer towards that goal, by adding small but incremental improvements to the basic design.
Design Philosophy
In designing JRC-1, my primary goal was to create a foundation on which future projects could be built. To this end the base board provides only the most basic features: RAM, ROM, serial ports, and an SPI port. Expansion slots and a user I/O port are provided to allow for incremental functionality to be added.
The other design goal that guided me with JRC-1 was to design something that, aesthetically, appears as if it could have originated in the 1980s. Thus all components are through-hole, and the entire design is based on 5V logic.
Feature List
- 65C816 CPU @ 8 MHz with plans to increase down the road if possible
- 1 MB of RAM
- 256 KB of ROM, capable of in-system reprogramming
- CPLD glue logic
- 65C22 VIAs, all pins brought out to user port
- SPI controller
- Two DB-9 serial ports
- SD card connector
- Three expansion connectors
- User I/O port
- JTAG port for in-circuit reprogramming of the CPLDs
- RESET and NMI switches
- Barrel jack for +5V DC power
- Power LED
Status
As of December 2022 the system has been running stable at 8 MHz for several months and the hardware design is considered finalized. Work continues on the JR/OS operating system.
Technical Details
Memory Map
|--------------------------------| $00/0000 | Base RAM (60K) | |--------------------------------| $00/F000 | I/O Area (2K) | |--------------------------------| $00/F800 | Boot ROM (2K) | |--------------------------------| $01/0000 | Extended RAM (944K) | |--------------------------------| $10/0000 | System ROM (256K) | |--------------------------------| $14/0000 | Reserved | |--------------------------------| $FF/FFFF
Address Decode Logic
|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------| | A20 | A19 | A18 | A17 | A16 | A15 | A14 | A13 | A12 | A11 | Mapping | |-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------| | 0 | 0 | 0 | 0 | 0 | 0 | x | x | x | x | RAM #1 | | 0 | 0 | 0 | 0 | 0 | 1 | 0 | x | x | x | RAM #1 | | 0 | 0 | 0 | 0 | 0 | 1 | x | 0 | x | x | RAM #1 | | 0 | 0 | 0 | 0 | 0 | 1 | x | x | 0 | x | RAM #1 | | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | I/O | | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | ROM | | 0 | 0 | 0 | 0 | 1 | x | x | x | x | x | RAM #1 | | 0 | 0 | 0 | 1 | 0 | x | x | x | x | x | RAM #1 | | 0 | 0 | 0 | 1 | 1 | x | x | x | x | x | RAM #1 | | 0 | 1 | X | X | X | x | x | x | x | x | RAM #2 | | 1 | 0 | 0 | X | X | x | x | x | x | x | ROM | |-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-------------|
I/O Registers
I/O space is mapped in the $Fx00 – $F7FF range in bank 0, where x = slot number. The on-board devices share 16-byte blocks in the “slot 0” range:
- $F000 – $F00F : VIA
- $F010 – $F01F : 65SPI
- $F020 – $F02F : 28L92 Dual UART
The remaining space in slot 0, as well as space for the non-existent slots 4-7. is reserved.
Expansion Slots
There are three expansion slots, each consisting of a 2×20 female header connector.
+----------+
+5V | 1 21 | +5V
GND | 2 22 | GND
A7 | 3 23 | D7
A6 | 4 24 | D6
A5 | 5 25 | D5
A4 | 6 26 | D4
A3 | 7 27 | D3
A2 | 8 28 | D2
A1 | 9 29 | D1
A0 | 10 30 | D0
NC | 11 31 | /NMI
PHI2 | 12 32 | NC
R/W | 13 33 | /RESET
/RD | 14 34 | NC
/RW | 15 35 | NC
NC | 16 36 | NC
NC | 17 37 | NC
/SLOTSEL | 18 38 | /IRQ
+5V | 19 39 | +5V
GND | 20 40 | GND
+----------+
Each slot is allocated 256 bytes of I/O space in the range $00/Fs00-FsFF, where s = slot number (1-3). When a slot is being accessed /SLOTSEL will go low and A0-A7 will hold the location being accessed.
The expansion bus A0-A7, D0-D7, PHI2, and R/W lines are directly connected to the CPU bus. Standard 65xx series peripherals can connect to them directly, using /SLOTSEL as a chip select. For other types of peripherals /RD and /WR can be used as read and write signals; they will go low during the PHI2 high phase. They are not, however, qualified by /SLOTSEL, so that signal must still be used as a master chip select.
The /IRQ, /NMI, and /RESET signals are open-drain and pulled up to +5V by 3.3K resistors. Peripherals with a totem pole /IRQ output (such as the 65C22S) will need a shottky diode in series with the /IRQ line.This is not ideal for high-speed interrupts but is necessary to make sure the /IRQ line is high even when no card is in the slot.